Importance

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Abstract

An improvement for obtaining synchronization to a chip-sequence signal. The chip-sequence signal has a plurality of chips, and is embedded in a spread-spectrum signal. A set of M shift registers stores a replica or delayed replica of the chip-sequence signal. Each shift register has a plurality of taps, which correspond to the plurality of chips. A plurality of comparators compares, with a delay of 1/M chip duration per shift register, the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in the set of M shift registers. From the comparison, the plurality of comparators generates, for each tap of the shift register, a plurality of compared values at each comparator of the plurality of comparators. A plurality of counters up and down counts, from each comparator, a respective plurality of compared values. The respective plurality of compared values appears at an output of a respective comparator of the plurality of comparators. The plurality of counters thereby generates a plurality of totals, respectively. A selector device selects a value from the plurality of totals. The selected value may be, by way of example, a largest value, a maximum likely value. The invention can be extended to one or more samples per chip, and each sample may have one bit for hard decision, or more bits for soft decision.

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First Claim