Cache coherency mechanism using an operation to be executed on the contents of a location in a cache specifying an address in main memory
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United States of America Patent
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Apr 8, 2003
Grant Date -
Jan 17, 2002
app pub date -
Mar 2, 1998
filing date -
Mar 5, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A computer system has a processor, a cache and a main memory. A cache coherency mechanism ensures that the contents of the cache are coherent with respect to main memory by the provision of cache coherency instructions which each specify: 1) an operation to be executed on the contents of a location in the cache; and 2) an address in main memory. The operation is executed for the contents of the location in the cache which could be filled by an access to that address in main memory if the executing process normally has access to that address in main memory, regardless of whether or not the contents of the specified address in main memory are held at that location in the cache. This provides an extra degree of freedom because it is not necessary for the cache coherency operation to be requested in respect of a particular address stored in the cache. The instruction can specify any address which would map onto that cache location.
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