Process for the formation of a spatial chip arrangement and spatial chip arrangement
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United States of America Patent
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Aug 8, 2006
Grant Date -
Jan 24, 2002
app pub date -
Sep 24, 2001
filing date -
Jun 28, 1996
priority date (Note) -
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Abstract
Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged transverse to the longitudinal extent of the carrier substrate.
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