Packet switch with one-stop buffer in memory with massive parallel access
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United States of America Patent
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Sep 25, 2007
Grant Date -
Jan 31, 2002
app pub date -
Jun 15, 2001
filing date -
Jun 16, 2000
priority date (Note) -
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Abstract
A broadband packet switch that handles all packets that arrive within the same frame time by simultaneously bit-pipelining the packets into different sections of the one-stop packet buffer through an input switch. Each packet remains in is selected section until its eventual exit from the buffer through an output switch. Access to the memory storage in which the packet buffer resides is not through a memory bus or buses, thereby engendering massive parallel access.
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