Importance

Loading Importance Indicators...

Abstract

A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and, when appropriate, generates an increment signal, and a second counter, clocked by the master clock, that increments in response to the increment signal. In a preferred embodiment, the resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits and a latch, e.g., a flip-flop, that latches the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate. Accordingly, counter chains of unlimited size that can be implemented in a field programmable logic array (FPGA) and that can run at the maximum clock rate of the FPGA can be realized.

Loading the Abstract Image...

First Claim