Method and apparatus for low overhead multithreaded communication in a parallel processing environment
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United States of America Patent
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Issued Date -
Jan 31, 2002
app pub date -
May 29, 2001
filing date -
Dec 28, 1999
priority date (Note) -
Abandoned
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Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
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