Complementary metal oxide semiconductor with improved single event performance

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United States of America Patent

PATENT NO 6653708
APP PUB NO 20020020858A1
SERIAL NO

09918208

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at -V (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.

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Patent Owner(s)

  • INTERSIL AMERICAS LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Doyle, Brent R Malabar, FL 8 36

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