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Abstract

In a non-volatile passive matrix memory device comprising an electrically polarizable dielectric memory material exhibiting hysteresis between first and second sets of addressing electrodes, the electrodes of the first set are word lines and the electrodes of the second set are bit lines of the memory device. A memory cell with a capacitor-like structure is defined in the memory material at the overlap between a word line and a bit line. The word lines are divided into segments with each segments sharing and being defined by adjoining bit lines and means are provided for connecting each bit line of a segment with a sensing means, thus enabling simultaneous connections of all memory cells of a word line segment for readout via the bit lines of the segment. Each sensing means senses the charge flow in a bit line in order to determine a logical value stored in a memory cell defined by the bit line. In a readout method for a memory device of this kind a word line of a segment is activated according to a protocol by setting its potential to a switching voltage of the memory cell during at least a portion of a read cycle, while keeping the bit lines of the segment at zero potential, during which read cycle a logical value stored in the individual memory cells is sensed by the sensing means. Use in a volumetric data storage apparatus with a plurality of stacked layers which each comprises a non-volatile passive matrix memory device.

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