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Abstract

A multiple output current mirror of improved accuracy suitable for use in a multi-level memory or analog applications is described. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror. By altering the physical arrangement of the pieces from one partial mirror to the next, variations in operating characteristics and manufacturing processes that are dependent upon positions are reduced since the variation in one partial mirror offsets that in another partial mirror. In an exemplary embodiment, the mirrored element, producing the reference current, and the mirroring elements in each of k branches are each composed of N transistors with a width w, giving an effective width W=Nw for each element and consequently a mirroring ration of 1 for all the branches. All of these N(k+1) transistors are physical placed in a linear arrangement of N partial current mirrors of (k+1) transistors each, where each partial mirror contains a transistor supplying part of the mirrored current and one transistor from each of the k branches mirroring it. Each of the N partial mirrors has its (k+1) elements arranged in a different permutation. The N=5, k=3 case is described in some detail.

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First Claim