Structure of wires for a semiconductor device

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United States of America Patent

SERIAL NO

09946366

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures. The method includes the steps of: forming an interlayer insulating structure on the semiconductor device; forming contact holes through the interlayer insulating structure to expose the impurity regions; lining contact-hole-portions of the interlayer insulating layer with portions of a barrier layer, respectively, such that the portions of the barrier layer contact the impurity regions; forming conductive pads on the portions of the barrier layer such that remainders of the contact holes are filled; and forming a wire layer on each one of the conductive pads.

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Patent Owner(s)

Patent OwnerAddress
LG SEMICON CO LTDNot Provided

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jung, Hyuck-Chai Chungcheongbuk-do, KR 13 43

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