Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit
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United States of America Patent
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Issued Date -
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app pub date -
Nov 26, 2001
filing date -
Nov 14, 1997
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals.
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