Method and circuitry for bank tracking in write command sequence
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United States of America Patent
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Oct 1, 2002
Issued Date -
N/A
app pub date -
Sep 21, 2001
filing date -
Jul 28, 2000
priority date (Note) -
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of addressable blocks. Control circuitry is provided to access the plurality of addressable blocks to perform a write or erase operation on memory cells contained in a first one of the plurality of addressable blocks. The control circuitry performs the write or erase operation in response to an externally provided command sequence and prohibits the write or erase operation if an externally provided bank address changes during the externally provided command sequence.
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