Address generator for local system memory in reconfigurable logic chip
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Sep 28, 2001
filing date -
Jun 30, 1999
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A reconfigurable logic system using reconfigurable functional units of the type having arithmetic logic units are associated with address generating memory units. The address generating memory units having address generators that can construct addresses for memory in the address generator memory units. This frees the reconfigurable functional unit from the need to construct a sequence of addresses for the memory unit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully