Storing a flushed cache line in a memory buffer of a controller
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United States of America Patent
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Oct 1, 2002
Grant Date -
Apr 11, 2002
app pub date -
Jul 29, 1999
filing date -
Jul 29, 1999
priority date (Note) -
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Abstract
Methods and devices to reduce processor-to-system memory access latency through the use of a memory buffer for the storage of cache lines flushed (cast out) from conventional level-1 (L1) and/or level-2 (L2) processor caches are described. The memory buffer, referred to as a cast-out cache, may be incorporated within a system controller and/or memory controller device.
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