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Abstract

A streaming memory controller has a time-division multiplexed interface to sources and destinations of data and a streaming interface to a memory. A unified address generator with look-aside registers is used to provide addresses for the memory. Each source and destination is identified by a context code that is used to index into a table of parameters. A processor loads initial values for the parameters that are then used by the unified address generator to access the appropriate area of memory for the context. Buffers hold data for read and write contexts. An arbiter specifies the context having the greatest requirement for memory access based on the context's buffer status. A sequencer sends streams of data for a specified context to memory until the interrupted by the arbiter.

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First Claim