Method for effective binary translation between different instruction sets using emulated supervisor flag and multiple page tables
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United States of America Patent
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N/A
Issued Date -
Apr 18, 2002
app pub date -
Apr 18, 2001
filing date -
Feb 17, 1999
priority date (Note) -
Abandoned
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Abstract
The present invention relates to a microprocessor based computer system having binary translation support to achieve high performance without compatibility problems. The computer system includes a support software layer that enables the execution of foreign application and operating system software without degradation during execution. The support software layer includes an emulated foreign supervisor flag and means for porting foreign software including the operating system to the host platform. The host platform includes host and foreign virtual space spaces and two page tables supported in hardware to minimize the time required for translation between virtual to physical addresses. A flag in a page table entry marks pages in the virtual memories having data that is accessible only to the host platform's supervisor. When the computer system processor is not operating in a foreign supervisor mode, an attempt to access the virtual space generates an exception trap.
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