High-voltage transistor with multi-layer conduction region
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United States of America Patent
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Oct 5, 2004
Issued Date -
N/A
app pub date -
Sep 20, 2001
filing date -
Nov 5, 1996
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Expired
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Abstract
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.
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