Importance

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Abstract

A circuit for electronically matching and synchronizing the receipt of data on transmission lines between two circuits. Data is transmitted from a sending circuit to a receiving circuit on transmission lines between the two circuits. A system clock is also provided to the receiving circuit to synchronize the receipt of data relative to the circuits on the chip. A variable delay circuit selectively provides the number of delayed clock cycles for the data. In one mode of operation, there is no delay in the clock cycles and the data is provided as an output on the subsequent system clock pulse after receipt by the receiving circuit. Under other conditions in a different mode, a delay is introduced in the data on the transmission line so that it is output to the receiving circuit one clock cycle delay from when it is received by the input terminal to the receiving circuit. The amount of delay is controlled by software that is programmable under user control.

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First Claim