Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection
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United States of America Patent
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-
Mar 22, 2005
Grant Date -
Jun 27, 2002
app pub date -
Jun 29, 2001
filing date -
Dec 22, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and associated apparatus is provided for improving the performance of a high speed memory bus using switches. Bus reflections caused by electrical stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a segmented bus wherein bus segments are connected through switches. The switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.
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