Logic emulator with routing chip providing virtual full-crossbar interconnect
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United States of America Patent
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N/A
Issued Date -
Jul 11, 2002
app pub date -
Jan 5, 2001
filing date -
Jan 5, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A hardware-based logic emulator uses routing chips to implement a virtual full-crossbar interconnect. Logic gates and some internal interconnection of the emulated design are programmed into field-programmable gate array (FPGA) logic chips. External interconnection of the logic chips is provided by routing chips. When the routing chips are also FPGA chips with a same number of I/O pins, the number of routing chips can be 1.5 times the number of logic chips. For L logic chips, the first L routing chips are column routing chips. The column routing chips connect to the same pin or pins of all the logic chips and make connections within a single column of a routing table. The other L2 routing chips are diagonal routing chips that connect to different pins on different logic chips. The diagonal routing chips make connections among logic chips along diagonals in the routing table.
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