I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
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United States of America Patent
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Jan 28, 2003
Issued Date -
N/A
app pub date -
Jul 25, 2001
filing date -
Dec 20, 1996
priority date (Note) -
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Abstract
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
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