Memory device
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United States of America Patent
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-
Dec 3, 2002
Grant Date -
Aug 1, 2002
app pub date -
Feb 28, 2002
filing date -
Nov 10, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
An addressable memory device for storing blocks of varying length, utilizes a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.
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