Slice interconnect structure
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Dec 19, 2002
app pub date -
Jun 3, 2002
filing date -
Jun 15, 2001
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A chip stack comprising at least two chip packages. Each of the chip packages comprises a packaged chip including a body defining an opposed pair of sides and having a plurality of leads extending outwardly from each of the opposed sides thereof. Each chip package further comprises a pair of rails which extend along respective ones of the opposed sides of the body. Each of the rails defines opposed top and bottom surfaces and includes top inner and outer pads disposed on the top surface and bottom inner and outer pads disposed on the bottom surface. The leads of the packaged chip within each chip package are electrically connected to respective ones of the top inner pads of each of the corresponding rails. In the chip stack, the chip packages are electrically connected to each other via the electrical connection of the leads of the packaged chip of one of the chip packages to respective ones of the bottom inner pads of the rails of the remaining one of the chip packages.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully