Digital phase locked loop
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United States of America Patent
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Feb 26, 2013
Issued Date -
N/A
app pub date -
Apr 24, 2002
filing date -
Apr 25, 2001
priority date (Note) -
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Abstract
A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.
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