Apparatus and method for interfacing with a high speed bi-directional network using a shared memory to store packet data
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United States of America Patent
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Jul 25, 2006
Grant Date -
Dec 19, 2002
app pub date -
May 15, 2001
filing date -
May 15, 2001
priority date (Note) -
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Abstract
A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device. The shared memory may comprise a plurality of banks of synchronous dynamic random access memory (SDRAM) devices, and may be used to store packet data in a network.
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