Arrangement of memory chip housings on a DIMM circuit board
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United States of America Patent
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Issued Date -
Dec 26, 2002
app pub date -
May 24, 2002
filing date -
May 25, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The invention relates to the arrangement of a plurality of memory chip housings, each having at least one memory chip arranged in the interior of the memory chip housing and having a plurality of pins, which are led out of the respective memory chip housing, on a DIMM circuit board which, on one long side, has a multipole contact rail for insertion into a base of a mother board, where the plurality of memory chip housings (2) [lacuna] arranged in two rows (6, 7) parallel to the long side (3) of the circuit board (1).
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