I/O interface structure
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United States of America Patent
Stats
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N/A
Issued Date -
Jan 2, 2003
app pub date -
Jun 3, 2002
filing date -
Jun 15, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A chip stack comprising at least two chip packages. Each of the chip packages comprises a packaged chip including a body defining an opposed pair of sides and having a plurality of leads extending outwardly from each of the opposed sides thereof. Each chip package further comprises a pair of rails which extend along respective ones of the opposed sides of the body. Each of the rails defines opposed top and bottom surfaces and includes top inner and outer pads disposed on the top surface and bottom inner and outer pads disposed on the bottom surface. A plurality of conductive bumps are formed on respective ones of the top outer pads of each of the rails of one of the chip packages. In the chip stack, the chip packages are electrically connected to each other via the electrical connection of the leads of the packaged chip of one of the chip packages to respective ones of the bottom inner pads of the rails of the remaining one of the chip packages which include the conductive bumps formed on respective ones of the top outer pads thereof.
First Claim
Family
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
STAKTEK GROUP L P | 8900 SHOAL CREEK SUITE 125 AUSTIN TX 78757 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Mantz, Frank E | Hawthorne, CA | 7 | 43 |
Roeters, Glen E | Huntington Beach, CA | 15 | 272 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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