PC16550D UART line status register data ready bit filter and latch
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United States of America Patent
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-
Jul 20, 2004
Grant Date -
Jan 9, 2003
app pub date -
Jun 7, 2001
filing date -
Jun 7, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A circuit for use with a PC16550D UART in 16450 polling mode that will filter DR bit oscillations. The circuit latches the value of the Line Status Register during the valid data portion of a LSR register read cycle, deasserts the read strobe, delays to allow the data bus values to float, applies the latched values of the LSR to the data bus, then asserts a ready signal to the microprocessor. If the UART access is not a read cycle to the LSR, the delay time is bypassed and the UART access cycle proceeds normally.
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