Detailed method for routing connections using tile expansion techniques and associated methods for designing and manufacturing VLSI circuits
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United States of America Patent
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Jul 13, 2004
Grant Date -
Jan 9, 2003
app pub date -
Apr 8, 2002
filing date -
Apr 6, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Disclosed herein is a method and associated apparatus for the design and manufacture of VLSI circuit which incorporates therein a method for routing connections between component tiles of the VLSI circuit being designed.
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