Process for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate for materials used to form the same and including an etch stop layer used for back side processing
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United States of America Patent
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Issued Date -
Jan 16, 2003
app pub date -
Jul 16, 2001
filing date -
Jul 16, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Highly controlled, highly aligned monolithic integration of devices in a high quality monocrystalline material layer (26) with vias (211, 231) fabricated in an underlying monocrystalline substrate (22) in a single monolithic three dimensional architecture (20, 34). Excellent compliancy is achieved in a monolithic semiconductor structure (20, 34) by processes described herein while at the same time fabrication of via openings (211, 231) in the monocrystalline substrate (20, 34) can be made in a controlled, aligned manner to the back side (263) of a high quality monocrystalline film (26). Conductive connections (219, 239) can be made to devices (271, 273) in the high quality monocrystalline layer (26) from its backside (263).
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