Inputs and outputs for embedded field programmable gate array cores in application specific integrated circuits
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United States of America Patent
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N/A
Issued Date -
Feb 6, 2003
app pub date -
Jul 24, 2002
filing date -
Jul 24, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An architecture to efficiently handle primary input and output signals for an embedded FPGA core in an ASIC is disclosed. Only the FPGA core is used without wire-bonding pads and pad ring found in conventional embedded FPGAs. The input and outputs of the embedded FPGA core can be made peripherally or at selected locations throughout the core to obtain high I/O-to-logic ratios and flexibility in I/O placement with high routability.
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