Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream
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United States of America Patent
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Dec 21, 2010
Grant Date -
Feb 27, 2003
app pub date -
Feb 14, 2002
filing date -
Feb 14, 2001
priority date (Note) -
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Abstract
A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
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