Architecture and related methods for efficiently performing complex arithmetic
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United States of America Patent
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Issued Date -
Mar 6, 2003
app pub date -
Mar 31, 2001
filing date -
Mar 31, 2001
priority date (Note) -
Abandoned
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Abstract
A hybrid summing module is presented, wherein the summing module is comprised of a hyperpipelined series of one or more of full-adders and associated registers, half-adders and associated registers, and registers receive select input(s) based, at least in part, on a bit-wise analysis of the input terms.
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