D-type latch with asymmetrical high-side MOS transistors for optical communication
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United States of America Patent
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N/A
Issued Date -
Mar 20, 2003
app pub date -
Sep 5, 2001
filing date -
Sep 5, 2001
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A D-type latch with current mode switching using MOS transistors for high speed data communication without excessive noise and poor waveform jittering and a method of quantitative circuit design of such D-type latch circuit is presented. With this method, a value of electrically equivalent channel geometry is selected for the input pair of MOS transistors and a different value of electrically equivalent channel geometry is selected for the feedback pair of MOS transistors so as to reduce the resulting amount of output signal ringing as compared to a similar D-type latch circuit where the corresponding values of electrically equivalent channel geometry are equal. Furthermore, a set of output signal waveforms from a divide-by-2 counter and a divide-by-16 counter using the D-type latch as their building block are presented.
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