US Patent Application No: 2003/0070,133

Number of patents in Portfolio can not be more than 2000

Familial correction with non-familial double bit error detection

ALSO PUBLISHED AS: 7634709

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Abstract

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Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses .times.4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a .times.4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
UNISYS CORPORATIONBLUE BELL, PA2777

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bauman, Mitchell A Circle Pines, MN 50 958
Rodi, Eugene A Minneapolis, MN 16 180

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (3)
7,065,697 Systems and methods of partitioning data to facilitate error correction 3 2003
7,051,265 Systems and methods of routing data to facilitate error correction 2 2003
7,437,651 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 4 2004
 
CHANG, YAO-CHUNG (1)
8,001,449 Syndrome-error mapping method for decoding linear and cyclic codes 0 2007
 
EMC CORPORATION (1)
7,275,201 Memory system 0 2005

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