US Patent Application No: 2003/0070,133

Number of patents in Portfolio can not be more than 2000

Familial correction with non-familial double bit error detection

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Abstract

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Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses .times.4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a .times.4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
UNISYS CORPORATIONBLUE BELL, PA1328

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bauman, Mitchell A Circle Pines, MN 49 1085
Rodi, Eugene A Minneapolis, MN 14 213

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (7)
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ADVANCED MICRO DEVICES, INC. (1)
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MAXTOR CORPORATION (1)
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ADAPTEC, INC. (1)
* 5,745,508 Error-detection code 30 1995
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
* 5,490,155 Error correction system for n bits using error correcting code designed for fewer than n bits 53 1992
 
RENESAS ELECTRONICS CORPORATION (1)
* 5,509,132 Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 68 1994
 
SUN MICROSYSTEMS, INC. (1)
* 5,781,568 Error detection and correction method and apparatus for computer memory 10 1997
 
ORACLE AMERICA, INC. (1)
* 6,574,746 System and method for improving multi-bit error protection in computer memory systems 9 1999
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
EMC CORPORATION (1)
* 7,275,201 Memory system 0 2005
 
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (6)
* 7,065,697 Systems and methods of partitioning data to facilitate error correction 3 2003
* 7,051,265 Systems and methods of routing data to facilitate error correction 2 2003
* 2005/0028,056 Systems and methods of routing data to facilitate error correction 0 2003
* 2005/0028,057 Systems and methods of partitioning data to facilitate error correction 8 2003
* 7,437,651 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 5 2004
* 2005/0289,440 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 4 2004
 
CHANG, YAO-CHUNG (2)
* 8,001,449 Syndrome-error mapping method for decoding linear and cyclic codes 0 2007
* 2009/0031,193 SYNDROME-ERROR MAPPING METHOD FOR DECODING LINEAR AND CYCLIC CODES 2 2007
* Cited By Examiner