Memory test apparatus and method of testing
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United States of America Patent
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N/A
Issued Date -
May 29, 2003
app pub date -
Aug 22, 2002
filing date -
Aug 24, 2001
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A memory tester for testing memory devices. The tester comprises a test header, an algorithmic pattern generator (APG) and a fault logic device. In the memory tester according to the invention successive data processing algorithms with minimum feedbacks are used. The APG generates test instructions wherein each instruction has fields controlling respective functional parts of the tester. The control signals are stored together with data signals in an instruction memory that provides high speed test pattern generation. For different memory types, the width of instruction memory varies.
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