System-on-chip breakpoint synchronization
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United States of America Patent
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N/A
Issued Date -
May 29, 2003
app pub date -
Nov 26, 2001
filing date -
Nov 26, 2001
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Handling breakpoints includes suspending execution of a peripheral and saving the state of the peripheral in response to a first signal indicating the execution of a breakpoint by a processor. Execution of the breakpoint by the processor is continued in response to receiving a second signal indicating that the state of the peripheral has been saved. The saved state of the peripheral is restored, in response to a third signal indicating the completion of the execution of the breakpoint by the processor.
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