Output buffer circuit, memory chip, and semiconductor device having a circuit for controlling buffer size
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United States of America Patent
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Jul 19, 2005
Grant Date -
Jul 3, 2003
app pub date -
Dec 26, 2002
filing date -
Dec 27, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a plurality of buffer size signals for determining the buffer size of the programmable impedance buffer synchronized with a first clock signal, and an impedance adjustment circuit configured to adjust the buffer size based on the buffer size signals in response to a level of an output data signal.
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