Semiconductor memory device in which source line potential is controlled in accordance with data programming mode
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United States of America Patent
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Feb 15, 2005
Grant Date -
Jul 10, 2003
app pub date -
Feb 28, 2003
filing date -
Jun 9, 2000
priority date (Note) -
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Abstract
A semiconductor memory device is provided with a memory cell, at least one select gate transistor and a circuit. The circuit is configured to rewrite data in the memory cell by applying a potential difference between the gate and the source or between the gate and the drain, which is larger than a power supply voltage. The circuit operates in a first data programming mode and a second data programming mode. A first command or a first combination is used for the first data programming mode. A second command or a second command combination is used for the second data programming mode. The source line is set to different potentials between the first data programming mode and the second data programming mode, in a period when data is rewritten, by using the different command or the different command combination.
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