FeRAM capacitor stack etch
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United States of America Patent
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Issued Date -
Jul 31, 2003
app pub date -
Oct 29, 2002
filing date -
Jan 31, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl.sub.3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF.sub.3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a 'shorting out' of the resulting FeRAM capacitor.
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