Multi-board connection system for use in electronic design automation
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United States of America Patent
Stats
-
Jun 22, 2004
Grant Date -
Jul 31, 2003
app pub date -
Mar 6, 2002
filing date -
Jul 30, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.
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