High data rate serial ferroelectric memory
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United States of America Patent
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Issued Date -
Aug 7, 2003
app pub date -
Feb 5, 2002
filing date -
Feb 5, 2002
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Abstract
A method for accessing data in a serial ferroelectric memory device including an input shift register coupled to a ferroelectric memory array including a plurality of memory cells arranged in a number of rows and columns thereof, the memory array having associated row, column, and segment decoders, includes clocking a serial address into the input shift register and starting a read access before the serial address is completely shifted into the input shift register. A read access can be started before an input bit sequence containing row, column, and segment decoder addresses has been completely clocked into the memory.
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