Emulation circuit with a hold time algorithm, logic analyzer and shadow memory

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20030154458A1
SERIAL NO

10356919

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
QUICKTURN DESIGN SYSTEMS, INC.SAN JOSE, CA10

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Butts, Michael R Portland, OR 40 2176
Kfir, Alon San Jose, CA 5 85
Shei, Swey-Yan Cupertino, CA 5 181
Wang, Ming Yang Lafayette, CA 17 310

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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QUICKTURN DESIGN SYSTEMS, INC. (2)
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* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

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