US Patent Application No: 2003/0154,458

Number of patents in Portfolio can not be more than 2000

Emulation circuit with a hold time algorithm, logic analyzer and shadow memory

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
QUICKTURN DESIGN SYSTEMS, INC.SAN JOSE, CA15

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Butts, Michael R Portland, OR 48 1871
Kfir, Alon San Jose, CA 9 58
Shei, Swey-Yan - 6 144
Wang, Ming Yang Lafayette, CA 29 200

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
SYNOPSYS, INC. (5)
6,823,497 Method and user interface for debugging an electronic system 97 2002
7,240,303 Hardware/software co-debugging in a hardware description language 34 2003
7,356,786 Method and user interface for debugging an electronic system 9 2004
7,506,286 Method and system for debugging an electronic system 12 2006
7,827,510 Enhanced hardware debugging with embedded FPGAS in a hardware description language 17 2007
 
FACEBOOK, INC. (2)
7,331,021 Fast/slow state machine latch 1 2005
7,459,936 Fast/slow state machine latch 0 2007
 
ALTERA CORPORATION (1)
7,191,426 Method and apparatus for performing incremental compilation on field programmable gate arrays 9 2004
 
CADENCE DESIGN SYSTEMS, INC. (1)
7,725,304 Method and apparatus for coupling data between discrete processor based emulation integrated chips 2 2006
 
INTEL CORPORATION (1)
8,412,981 Core sparing on multi-core platforms 2 2006
 
L-3 COMMUNICATIONS CORPORATION (1)
8,751,990 System for determining median values of video data 0 2008
 
QIMONDA AG (1)
7,882,324 Method and apparatus for synchronizing memory enabled systems with master-slave architecture 0 2007
 
S2C INC. (1)
7,353,162 Scalable reconfigurable prototyping system and method 16 2005
 
SAMSUNG ELECTRONICS CO., LTD. (1)
8,275,588 Emulation system and driving method thereof 0 2009
 
SPINGSOFT, INC. (1)
8,255,853 Circuit emulation systems and methods 0 2010
 
TEKTRONIX, INC. (1)
8,736,300 In-circuit data collection using configurable selection networks 0 2012
 
TEXAS INSTRUMENTS INCORPORATED (1)
7,676,697 Using a delay line to cancel clock insertion delays 1 2006
 
XILINX, INC. (1)
7,506,298 Methods of mapping a logical memory representation to physical memory in a programmable logic device 1 2006