Bit error measuring apparatus and trigger signal generating circuit for the bit error measuring apparatus
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United States of America Patent
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Issued Date -
Aug 28, 2003
app pub date -
Feb 20, 2003
filing date -
Feb 25, 2002
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
The trigger signal generating circuit includes a comparing section for comparing a predetermined waiting pattern with a parallel pattern which is outputted from an M sequential random pattern generator, before carrying out multiplexing, a first retiming section for carrying out a retiming with respect to a pattern coincident signal which is outputted from the comparing section, in accordance with a low speed clock signal, and a second retiming section for carrying out a retiming with respect to a retiming signal which is outputted from the first retiming section, in accordance with a high speed clock signal, wherein the second retiming section outputs an output signal used as the trigger signal.
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