Importance

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Abstract

Clock recovery circuitry for recovering a clock signal from a data signal is disclosed. The clock recovery circuitry comprises sampling unit (46) for sampling the data signal at a plurality of sampling points, bit reversal detecting unit (48) for determining a sampling point at which the data signal changes state, selecting unit (50) for selecting a phase from amongst a plurality of candidate phases based on a sampling point at which the data signal is determined to change state, and phase setting unit (38) for setting the phase of the clock signal. The circuitry may be used to produce an estimate of a desired phase of the clock signal for supply to a phase locked loop. This can allow the phase locked loop to be brought quickly into lock.

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First Claim