Reconfigurable control processor for multi-protocol resilient packet ring processor
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United States of America Patent
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Issued Date -
Sep 18, 2003
app pub date -
Jan 15, 2003
filing date -
Jan 15, 2002
priority date (Note) -
Abandoned
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Abstract
A method and system for adaptive multi-protocol resilient packet ring (RPR) processing are provided. The present invention provides optimal handling operations targeted for both legacy and evolving RPR functions related to topology discovery, fairness algorithms, and control-packet manipulation. Further, the present invention utilizes out-band paths, unique data and instruction memory constructs, and pipeline and multi-thread features to provide wire-rate performance. In one embodiment, a system of the present invention includes instruction memory; a fetch unit associated with instruction memory; a decode unit associated with the fetch unit; at least one execution unit associated with the decode unit; a load/store unit associated with the at least one execution unit; and data memory associated with the load/store unit.
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