Instruction issuing device and instruction issuing method
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United States of America Patent
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Issued Date -
Sep 25, 2003
app pub date -
Apr 30, 2002
filing date -
Mar 19, 2002
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A first detecting circuit detects a register depending directly on a load instruction. A second detecting circuit detects indirect dependencies of plural stages between all instructions in a state of execution and all load instructions of the respective stages of a pipeline, in accordance with cache miss signals and output signals of the first detecting circuit.
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