High speed switching MOSFETS using multi-parallel die packages with/without special leadframes
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United States of America Patent
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Feb 27, 2007
Grant Date -
Oct 2, 2003
app pub date -
Jul 30, 2002
filing date -
Mar 31, 2002
priority date (Note) -
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Abstract
This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.
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