Module for generating circuits for analysing bit strings inside data cells, method for generating this type of circuit and relative circuit
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United States of America Patent
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Issued Date -
Oct 2, 2003
app pub date -
Jan 29, 2003
filing date -
Aug 1, 2000
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
This invention refers to a module 10 for generating integrated circuits suitable for analysing and validating bit strings inside telecommunications data cells, to the method for defining the structure and characteristics of such module and the integrated circuits that can be generated and to the integrated circuit that can be obtained with such module 10. The module 10, called parser, is parametric and makes it possible to generate parser circuits for many protocols because of such characteristic; the module 10, also, makes it possible, by means of a module REGFILE_2OUT 12, to generate programmable parser circuits and, by means of a module LOGIC_OPER 22 that can generate several analysis and validation devices, to execute in parallel bit string analysis inside telecommunications data cells.
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