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Abstract

In accordance with the present invention, a memory cell includes both non-volatile and SRAM cells. The non-volatile memory cell includes two MNOS transistors forming a differential pair. The SRAM cell includes a pair of MOS select transistors and a pair of cross-coupled MOS transistors. The MOS select transistors are adapted to couple the true and complement bitlines associated with the memory cell to various terminals of the cross-coupled MOS transistors, thereby to load data into the SRAM. During power-off, data is loaded from the SRAM into the non-volatile memory cell. During a subsequent read of the non-volatile memory cell, the SRAM is reloaded with data it had prior to the power-off. Because the MNOS transistors of the non-volatile memory cell operate differentially, data read errors caused by over-erase are reduced. Because the voltages applied during programming and erase cycle of the non-volatile memory cell are relatively small, the memory cell consumes relatively small amount of power.

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First Claim